1. Field of the Invention
The present invention relates to switching DC-to-DC converters, and to switching controllers for use in such converters.
2. Description of the Related Art
One type of conventional switching power supply circuitry which employs voltage feedback to achieve output voltage regulation is the DC-to-DC converter of FIG. 1, which includes current mode switching controller chip 1, and buck converter circuitry external to the controller chip. The buck converter circuitry of FIG. 1 comprises NMOS transistor N1 (which functions as a power switch), inductor L, current sense resistor Rsns, capacitor C, and feedback resistor divider RF1 and RF2, connected as shown. The FIG. 1 circuit produces a regulated DC output voltage Vout across load RLOAD, in response to input DC voltage Vin.
Controller chip 1 implements a control signal channel which generates pulse width modulated power switch control signals (xe2x80x9cPWM switch controlxe2x80x9d signals) for power switches N1 and N2 in response to a ramped voltage (Vosc) and a train of set pulses (generated by oscillator and ramped voltage generation circuit 2), a feedback signal (supplied from Node A to the inverting input of error amplifier 10) indicative of the DC-to-DC converter""s output potential, and a feedback signal indicative of current through sense resistor RSNS. One of the PWM switch control signals (asserted at the xe2x80x9cQxe2x80x9d output of reset dominant latch 89) controls the gate of power switch N1. The other PWM switch control signal (asserted at the output of AND gate 102) controls the gate of power switch N2.
Typically, each PWM switch control signal is a binary signal having periodically occurring leading edges, and trailing edges which occur at times determined by the instantaneous value of the feedback signals. Specifically, the feedback provided from sense resistor RSNS to current sense amp 11 of controller 1 is a ramped voltage which is compared (in comparator 106) with a reference potential (100 mV in the specific implementation shown in FIG. 1). The output of comparator 106 is provided to one input of AND gate 100. The feedback signal indicative of the DC-to-DC converter output potential is asserted to the inverting input of error amplifier 10, and the noninverting input of error amplifier 10 is at a reference potential VREF. The output of error amplifier 10 is compared (by comparator 8) with the ramped voltage VOSC summed with the current feedback signal from current sense amp 11, and the output of comparator 8 is provided to the other input of AND gate 100. The output of AND gate 100 is a train of reset pulses which drive one input of OR gate 113. The other input of gate 113 is driven by the output of skip comparator 114 (which compares the output of error amplifier 10 and threshold potential Vth). The output of OR gate 113 is employed to reset the latch 89. The described use of the voltage VOSC improves stability through a technique known as xe2x80x9cramp compensation.xe2x80x9d The value of the output of current sense amplifier 11 depends on the current through sense resistor RSNS (and thus the current through inductor L).
Controller chip 1 includes oscillator and ramped voltage generation circuit 2, comparators 8, 106, 107, and 114, reset dominant latch 89 (having a xe2x80x9csetxe2x80x9d terminal coupled to receive the xe2x80x9csetxe2x80x9d pulse train from circuit 2, a xe2x80x9cresetxe2x80x9d terminal coupled to the output of OR gate 113, an output coupled to the gate of switch N1 and to the xe2x80x9csetxe2x80x9d terminal of latch 91, and an inverted output coupled to one input of AND gate 102), latch 91 (having a xe2x80x9cresetxe2x80x9d terminal coupled to the output of comparator 107 and an output coupled to the other input of AND gate 102), error amplifier 10 (having an inverting input coupled to Node A and a non-inverting input maintained at reference potential Vref), current sense amplifier 11 (having a non-inverting input coupled to the node between inductor L and resistor RSNS, an inverting input coupled to the buck converter circuitry""s output node, and an output coupled to an input of comparator 106 and to summing node B). The other input of comparator 106 is maintained at a reference potential (which is 100 mV above ground in an implementation of the FIG. 1 circuit, as indicated in FIG. 1).
Reference potential Vref (asserted to the noninverting input of error amplifier 10) is typically set by control bits and is normally not varied during use of the circuit. In order to set (or vary) the regulated level of the output voltage Vout, resistors RF1 and RF2 with the appropriate resistance ratio RF1/RF2 are coupled to Node A.
Oscillator 2 asserts a clock pulse train (having fixed frequency and waveform as indicated) to latch 89, and as long as the reset input to latch 89 is low, each positive-going leading edge of this pulse train sets latch 89. Each time latch 89 is set, the potential asserted by latch 89 (the Q output of latch 89) to the gate of transistor N1 causes transistor N1 to turn on. Although transistor N1 turns on at times in phase with the periodic clock pulse train, it turns off at times (determined by the feedback signals, reference potential Vref and the compensating ramp) that have arbitrary phase relative to the pulses of the periodic clock pulse train asserted to latch 89 by oscillator 2.
Each time latch 89 is set, the output of latch 89 sets latch 91, but since the inverted output of latch 89 goes low, the output of AND gate 102 goes low (thus preventing transistor N2 from turning on). After latch 89 has been set and before latch 89 is reset (while transistor N1 is on), transistor N2 remains off since the inverted output of latch 89 is low, forcing the output of AND gate 102 low. Then, in response to each reset of latch 89, the inverted output of latch 89 goes high, thus forcing the output of AND gate 102 high and turning on transistor N2. After N2 has been turned on (and N1 has been turned off), the output of comparator 107 goes high (to reset latch 91 and turn off transistor N2) when the current IIND through inductor L falls to zero. This sequence repeats during normal (continuous mode) operation of the FIG. 1 circuit (for as long as the output of comparator 106 remains high). During continuous mode operation of FIG. 1, the output of comparator 106 is high (a logical xe2x80x9conexe2x80x9d), so that the reset times of latch 89 are determined by the output of comparator 8 (latch 89 is reset each time VOSC rises above the output of error amplifier 10).
When the current IIND through inductor L falls below a threshold value (e.g., under light load conditions), the output of current sense amplifier 11 drops below the 100 mV threshold which causes the output of comparator 106 to go low. If this occurs, latch 89 cannot be reset until the output of amplifier 11 rises back above 100 mV. Transistor N1 remains on, until the outputs of both comparator 106 and comparator 8 are high. Under light load conditions, this causes Vout to rise and the output voltage of error amplifier 10 to fall. When the output voltage of error amplifier 10 (at node B) falls below Vth, comparator 114""s output is held high, which drives the output of OR gate 113 high. This forces a constant high signal at the reset input of latch 89, and prevents latch 89 from setting. In this way, the converter is forced to operate in a pulse skipping mode (in which it skips pulses). In the pulse skipping mode, both transistors N1 and N2 remain off (for two or more cycles of Vosc) until latch 89 reset is released (i.e., until the output of OR gate goes low).
Upon entry into the pulse skipping mode (sometimes referred to as the xe2x80x9cskip modexe2x80x9d), the reset input of latch 89 is held high by OR gate 113 (which forces the latch 89 to be reset), N1 is forced off by latch 89, and N2 turns off and remains off once the inductor current IIND falls to zero. The pulse skipping mode ends, and the FIG. 1 circuit returns to continuous mode operation, only when the output of error amplifier 10 rises above a threshold value so as to cause the output of comparator 114 to go low. When the output of comparator 114 is low, the output of comparator 8 again controls the resetting of latch 89 as described.
Oscillator 2 asserts ramped voltage Vosc (which periodically increases at a fixed ramp rate and then decreases, with a waveform as indicated) at a second output thereof.
In some variations on the FIG. 1 circuit, logic circuitry is provided to prevent transistor N2 from turning off when the inductor current reaches zero amps, and to prevent comparator 114 from preventing latch 89 from setting (thus forcing the circuit to operate always in the continuous mode) when an appropriate control signal is asserted to the logic circuitry.
Skip mode operation of the FIG. 1 converter achieves more efficient operation under low load conditions than would continuous mode operation. However, the conventional design of FIG. 1 is subject to several limitations and disadvantages, including in that the FIG. 1 requires a sense resistor (RSNS) external to the controller chip (chip 1).
Multi-channel variations on the circuit of FIG. 1 can readily be implemented by those of ordinary skill in the art. Other conventional DC-to-DC converters include a switching controller chip, and power channel circuitry (e.g., boost converter circuitry) other than buck converter circuitry external to the controller chip. Some conventional multi-channel DC-to-DC converters employ switching controllers which receive only feedback indicative of the potential at the converter""s output node and do not receive feedback indicative of the current through the inductor of each individual power channel (e.g. the feedback supplied to current sense amplifier 11 of FIG. 1). Another conventional DC-to-DC converter includes a switching regulator chip (which performs the functions of a switching controller and also includes internal power switches), and additional circuitry external to the regulator chip (in contrast with a converter that includes a controller chip having internal control signal channel circuitry, and external power channel circuitry outside the controller chip). It is contemplated that all such conventional converters can be improved in accordance with the invention.
In preferred embodiments, the invention is a switching DC-to-DC converter having a controller which generates power switch control signals for at least one power channel, and external circuitry (having at least one power channel including a first power switch, an inductor coupled between the first power switch and the converter""s output node, and typically also a second power switch coupled with the first power switch and the inductor). The external circuitry is external to the controller, the controller is typically implemented as an integrated circuit, and each power switch is typically an MOS transistor. The converter is configured to operate in a continuous mode when the current through the inductor remains above zero. In typical implementations, during the continuous mode, the inductor current remains positive as it rises and falls in response to the first and second power switches turning on and off 180 degrees out of phase with respect to each other, with the first power switch switching on and off once per switching cycle except in preferred implementations which include cycle-skipping circuitry operable in the continuous mode to cause the first power switch and the second power switch to remain off during a cycle under the condition that the converter""s output potential rises above a threshold potential.
The converter is also configured to enter a discontinuous mode of operation when the inductor current falls to zero (which occurs when the load current is below a threshold value), and to leave the discontinuous mode and resume continuous mode operation when the inductor current rises above zero. The main difference between the continuous and discontinuous modes of operation is as follows. In the continuous mode, the first power switch has a duty cycle which is independent of the current drawn from the converter by the load. Also, the second power switch is turned on when the first power switch turns off, and remains on until the first power switch is turned on again. In the discontinuous mode, the first power switch has a duty cycle which is dependent on load. Also in the discontinuous mode, the second power switch is turned on when the first power switch turns off, and is turned on when the inductor current reaches zero amps. The discontinuous mode is more efficient than the continuous mode under conditions of low load current.
In preferred implementations, the discontinuous mode is a pulse skipping mode (referred to herein as a discontinuous skip mode) in which the first power switch has a duty cycle which is the longer of a minimum duty cycle and a discontinuous mode duty cycle (the load-dependent duty cycle under which the converter would operate, when asserting the same output potential in response to the same input potential, if the circuitry for imposing the minimum duty cycle were disabled or omitted). The minimum duty cycle is defined as a proportion of the continuous mode duty cycle under which the converter would assert the same output potential (as it does in the discontinuous skip mode) in response to the same converter input potential. In a typical implementation (to be described with reference to FIG. 2), the minimum duty cycle is 85% of the continuous mode duty cycle. In the discontinuous skip mode, when the first power switch operates with the minimum duty cycle, the converter""s output voltage rises, and the error amplifier""s output potential decreases.
Preferably, the controller includes cycle-skipping circuitry operable in the discontinuous skip mode to cause the first power switch to remain off for at least one cycle under the condition that the converter""s output potential rises above a threshold. In preferred embodiments, the cycle-skipping circuitry includes a comparator which compares an error amplifier output (indicative of the converter""s output potential) with a threshold potential, and logic circuitry (e.g., an AND gate coupled to the output of the comparator) which asserts a latch-clearing signal once per switching cycle when the comparator output indicates that the converter""s output has risen above the threshold. A latch (which controls the times at which the first power switch turns off and on) receives each latch-clearing signal and causes the first power switch to skip the next cycle in response to each latch-clearing signal. In some embodiments, the cycle-skipping circuitry is operable in both the continuous mode and the discontinuous skip mode.
Other aspects of the invention are a switching controller for use in such a converter (the controller having both a discontinuous mode and a continuous mode of operation), and a method for generating power switch control signals for a DC-to-DC converter in a discontinuous mode of operation (without use of an external sense resistor) under conditions of low load current, with the converter otherwise operating in a continuous mode. Typically, a switching controller that embodies the invention is implemented as an integrated circuit, and each power switch is external to the controller chip and coupled to receive a power switch control signal from the controller chip.